Generally, as a chip size of a semiconductor memory increases, a length of a data line that is used for transporting data increases as well. Accordingly, a current sense amplifier, which may be relatively less influenced from capacitive loads of data lines as compared to a voltage sense amplifier, may be used in semiconductor memory devices. In a current sense amplifier, because it does not have voltage a difference on data lines, the data lines need not be equalized even when different data are successively transferred. Therefore, the current sense amplifier may be advantageously applied when an operation speed of the memory increases.
Unfortunately, conventional current sense amplifiers may be restricted to low voltage operation environments. Moreover, conventional current sense amplifiers may experience degradation in operation stability and/or sensing delay increases.
FIG. 1 is a circuit diagram of a conventional current sense amplifier circuit that is configured for use in a semiconductor memory device, such as dynamic random access memory (hereinafter, referred to as DRAM) and the like. Referring to FIG. 1, a configuration is shown in which a bit line sense amplifier (B/L S/A) 10, a current sense amplifier 20, and a differential amplifier 30 are connected. If data in a memory cell (not shown), which is sensed as data 0 or 1 by the bit line sense amplifier 10 in a read operation mode, is sent to a pair of data lines DL and /DL, then the current sense amplifier 20, which operates in response to sensing enable signals EN and ENB, current-senses the data to provide current sensing outputs SO and /SO. The current sensing outputs SO and /SO of the current sense amplifier 20 are applied to inputs of the differential amplifier 30, are voltage-amplified, and are transmitted to a data output circuit (not shown).
FIG. 2 is a circuit schematic that illustrates exemplary operations of a conventional current sense amplifier circuit, which is used in a DRAM application. The data in the memory cell sensed by the bit line sense amplifier 10 is transmitted to the pair of data lines DL and /DL when column selection lines CSL are enabled. In FIG. 2, it is assumed that a difference between currents generated by the bit line sense amplifier 10 is denoted by I, and CIO is denoted as a capacitive load of the pair of data lines DL and /DL. In the figure, P type MOS transistors M5 and M6 respectively connected to the bit line pair BL and /BL are load transistors and serve to provide an operation current to the current sense amplifier 20. Assuming that each of the currents flowing through the P type MOS transistors M5 and M6 is i, a current flowing through a node A, which will be a first output of the current sense amplifier 20, is i−I, and a current flowing through a node B, which will be a second output, is i. That is, a difference between the currents flowing through the node A and the node B is I.
If the P type MOS transistors M1 and M3 constituting the current sense amplifier 20 operate in a saturation area and have the same size, voltage differences between the gates and the sources of the MOS transistors M1 and M3 become approximately identical to each other. That is, VGS1=VGS3=V1. In the same way, if the P type MOS transistors M2 and M4 operate in a saturation area and have the same size, then VGS2=VGS4=V2. Because a selection signal YSEL is zero when the column selection line CSL operates, the input node voltages on the column selection lines CSL are each V1+V2 and have about the same voltage. As a result, because the currents into the column selection lines CSL have a difference of I but the voltages on the input nodes are equally maintained, there is virtually no voltage difference generated. As a result, the input resistance RIN of the column selection line CSL becomes approximately zero. Accordingly, the pair of data lines DL and /DL are able to transmit the data in a full current mode.
That is, RIN=ΔvIN/ΔiIN=0/I=0. When RIN is expressed by transconductance of each of the transistors, the following equation is obtained: RIN={2(gm34−gm12)}/gm12×gm34. In the foregoing equation, gm is the transconductance of the MOS transistors. Assuming a symmetrical design, gm1=gm2=gm12 and gm3=gm4=gm34. To meet a condition that RIN is zero, gm12=gm34. That is, the transconductance of the MOS transistors M1 and M2 constituting the cross-coupled latch circuit is the same as the transconductance of the current source transistors M3 and M4 preventing a latch operation.
If RIN<0, namely, the transconductance of the N type MOS transistors M1 and M2 constituting the cross-coupled latch circuit is larger than that of the current source transistors M3 and M4 preventing the latch operation, then the column selection line CSL may have similar properties as a latch, which may degrade operation stability.
On the other hand, if RIN>0, then the column selection line CSL may operate in a voltage operation mode. Unfortunately, data transmission speed may be reduced because a voltage difference is generated between two inputs of the column selection line CSL.
A size ratio of the P type MOS transistors M1 and M2 and the P type MOS transistors M3 and M4 may be adjusted for the column selection line CSL to have zero input resistance RIN. However, although RIN=0 may be met under particular conditions, variation of the operation voltage or the operation temperature may prevent the result of RIN=0 from being met. This is because gm12 and gm34 are not always maintained in the same ratio.
Operation at low voltage, however, may prevent each of the transistors of the column selection line CSL from maintaining its saturation mode, which may result in a greater change in RIN. Because the column selection line CSL has, as a required minimum voltage level, a voltage drop from the bit line sense amplifier to the input of the column selection line CSL plus a threshold voltage of the transistor M1 plus a swing voltage at the node A plus a threshold voltage of the transistor M3, the operation voltage of 2V or less allows the transistors of the column selection line CSL to be operated out of the saturation mode. Accordingly, ideal column selection line CSL functionality may be lost.
Referring back to FIG. 1, operations of a non-ideal column selection line CSL will now be described. Generally, to avoid an unstable operation of the column selection line CSL, RIN is initially designed to have a value a little greater than zero. This allows RIN to maintain a positive value even when process, voltage, and temperature (hereinafter, PVT) variation occurs. Accordingly, a voltage changes with a current change at the input node of the column selection line CSL. When a current flows in the bit line sense amplifier 10 of FIG. 1, the voltage on the complementary data line/DL becomes greater than the voltage on the data line DL if RIN is greater than zero. Accordingly, the load currents IM5 and IM6 generated from the P type MOS transistors M5 and M6 for load current generation are no longer the same. That is, if the voltage on the complementary data line/DL is higher than the voltage on the data line DL, then the load current IM6 becomes less than the load current IM5. Two problems may arise in this case.
First, the current difference generated between the two nodes of the current sense amplifier 20 is given by /ISO−ISO=IM6−(IM5−I). Because the current IM6 is less than the current IM5, the current difference value is less than I. Because the current difference I generated by the bit line sense amplifier 10 is not entirely delivered to the current sense amplifier 20, the voltage swing on the output nodes SO and /SO resulting from the current difference decreases. Further, because the voltages on the output nodes SO and /SO become inputs to the differential amplifier 30 connected to a next stage, it may degrade the operation speed of the differential amplifier.
Second, if data from the different bit line sense amplifiers 10 are successively sensed, then a sensing speed may be reduced when the data from the bit line sense amplifiers 10 are the same. Consider the case where several input/output (I/O) lines are connected to the pair of data lines DL and /DL and are connected to one current sense amplifier to perform the sensing operation and different column selection lines CSL are selected for performing the successive operation. If the current difference, /ISO−ISO=IM6−(IM5−I) is generated at both sides and then a first column selection line CSL is off to select another column selection line CSL. As a result, I=0 and the current difference between both sides becomes IM6−IM5. Accordingly, the current takes an opposite direction and the voltages on the outputs SO and /SO also vary. As the voltages on the pair of data lines DL and /DL become gradually the same, the current difference vanishes. In the case where the subsequent column selection line CSL is enabled and the current in the bit line sense amplifier 10 is again supplied to the current sense amplifier 20 before the voltages on the pair of data lines DL and /DL become the same, the current direction must change again if the data of the bit line sense amplifier 10 is identical to previous data. Because the voltages on the sensing outputs SO and /SO change, sensing delay may increase.
Because the problems discussed above may arise when the input resistance RIN of the column selection line CSL is larger than zero, the input resistance RIN may be designed to be zero if possible.
FIG. 3 is a diagram that illustrates simulation waveforms of signals related to a sensing output of FIG. 1. There is shown in the figure results obtained by simulation-measuring voltages on the pair of data lines DL and /DL that are the inputs to the current sense amplifier, the voltage on the sensing outputs SO and /SO, and the voltage on the output OUT of the differential amplifier 30 while the bit line sense amplifier 10 data are changed. An abscissa axis denotes time and an ordinate axis denotes voltage.
FIG. 4 is a graph that illustrates maximum voltage difference between a pair of data lines generated when external environment factors change in the circuit of FIG. 1. In FIG. 4, there is shown a measured and plotted result of a maximum voltage difference between the pair of data lines DL and /DL, where VDD=1.6V, 2V, 2.5V and 3V and the temperature is −5° C., 50° C. and 110° C. Here, an abscissa axis denotes voltage and an ordinate axis denotes voltage difference. It can be seen that as the operation voltage is reduced and in turn the input resistance RIN of the column selection line CSL increases, the voltage difference between the pair of data lines DL and /DL increases. If the transistors constituting the current sense amplifier 20 are changed in size for the input resistance RIN of the column selection line CSL at the low voltage to be zero, then the input resistance RIN becomes negative (−) when VDD is high, which may cause a stability problem.
FIG. 5 shows results obtained by simulation-measuring a time beginning from a time of enabling the column selection line CSL to a time until the output OUT node reaches 500 mV, namely, a sensing delay in the circuit of FIG. 1. As the operation voltage decreases, the speed of the differential amplifier 30, which receives as its inputs the outputs from the current sense amplifier 20, is reduced. In addition, the output voltage swing of the current sense amplifier 20 (voltage swing at the SO and /SO nodes) may be reduced depending on the increase of the input resistance RIN of the column selection line CSL, which may cause a problem in that the sensing delay further increases. This is because the current sense amplifier needs an operation voltage, which is greater than the voltage drop from the output of the bit line sense amplifier 10 to the input of the current sense amplifier 20 plus the threshold voltage of the M1 transistor plus the swing voltage at the node A plus the threshold voltage of the M3 transistor.
It is known that the P type MOS transistors M3 and M4 shown in FIGS. 1 and 2 may be replaced by N type MOS transistors and the gate bias may be set to a constant voltage. Such technology is described, for example, by J. Y. Sim et al., in Double boosting, Hybrid Current sense Amplifier, and Binary Weighted Temperature Sensor Adjustment Schemes for 1.8V 128 Mb Mobile DRAMs Symp. in VLSI circuit digest of Technical Papers, 2002, pp 294–297. This may allow the threshold voltage drop in the P type MOS transistors M3 and M4 to be reduced or eliminated, resulting in an enhanced low voltage operation characteristic. Thus, because a phenomenon that the input resistance RIN suddenly increases at a low voltage may be reduced, an operation characteristic may be enhanced. However, there is still a problem that the change in the input resistance RIN becomes greater because the PMOS transistors constituting the cross-coupled latch and the NMOS transistors for latch prevention have a current pass characteristic difference therebetween due to PVT variation.